1. Field of the Invention
The present invention relates generally to a semiconductor device and a method of manufacturing the same, and more particularly to an insulative film of a novel structure formed on a semiconductor substrate and a method of manufacturing the same.
2. Description of the Related Art
A semiconductor device such as an LSI is constituted by a number of circuit elements formed on a semiconductor substrate. In this case, insulative layers having various functions are used in the semiconductor device. For example, the insulative layers are used as a gate insulating layer in a MOSFET, a field insulation layer for separating devices, an interlayer insulating layer for mutually insulating wires (including electrodes) arranged on the same plane or upper and lower wires, or a passivation layer for protecting wires and others.
It is necessary that the insulative layer used in the semiconductor have the following features: high quality of layer, absence of pin holes, high withstand voltage, and low moisture absorption property. On the other hand, high integration density is required for the semiconductor device. To meet this requirement, the width of a wire has been reduced and wires have been formed in multi-layers. In this case, if the interlayer insulative layer under the wire has an uneven surface, severing of wire may occur; thus, it is desirable to flatten the surface of the interlayer insulative layer.
The insulative layer used in the semiconductor device is made mainly of a silicon oxide or a silicon nitride. The characteristics of silicon oxides may vary depending on the methods of producing them. The silicon oxides are classified into: a CVD SiO.sub.2 layer formed by means of a CVD process, an SOG (Spin on Glass) layer formed by coating a liquid-phase silicon oxide on a substrate, and a thermal oxide layer formed by means of a thermal oxidizing process.
A conventional semiconductor device using an SOG film as an interlayer insulative film will now be described with reference to FIG. 1.
An insulative layer 2 made of a silicon oxide or the like is formed on a silicon substrate 1. First aluminum wires 11A and 11B are formed on the insulative layer 2. A CVD SiO.sub.2 layer 4 is formed on the aluminum wires 11A and 11B. The surface of the layer 4 is made sharply uneven. To correct the unevenness, an SOG layer 6 is formed. The surface of the SOG layer 6 is flattened. A CVD SiO.sub.2 layer 5 is deposited on the SOG layer 6.
In the semiconductor device shown in FIG. 1, an interlayer insulative layer is composed of the CVD SiO.sub.2 layers 4 and 5 and SOG layer 6. The voltage-withstanding property of the interlayer insulative layer is ensured mainly by the CVD SiO.sub.2 layers 4 and 5, and the flatness of the interlayer insulative layer is ensured mainly by the SOG layer 6. A though-hole 8 reaching the aluminum wire 11B of the first layer is formed in the interlayer insulative layer. Second aluminum wires 21A and 21B are formed on the interlayer insulative layer. The first aluminum wiring 11B and the second aluminum wiring 21B are electrically connected to each other through the through-hole 8.
Although the interlayer insulative layer having the above structure has excellent flatness, the SOG layer 6 has moisture-absorbent property; therefore, a baking step or the like must be performed in the manufacturing process. If such a step is not performed, water exudes from the SOG layer 6, for example, when the through-hole 8 is formed. As a result, the electrical conduction between the first aluminum wire 11A and the second aluminum wire 21B is degraded or lost.
Next, a conventional semiconductor device, which does not use an SOG layer as an interlayer insulative layer, will now be described with reference to FIG. 2.
An insulative layer 2 formed of silicon oxide is coated on a silicon substrate 1. First aluminum wires 11A and 11B are formed on the insulative layer 2. Using a plasma CVD process, a CVD SiO.sub.2 layer 4 is deposited on the first aluminum wires 11A and 11B. The surface of the CVD SiO.sub.2 layer 4 is made sharply uneven. In order to flatten the surface of the CVD SiO.sub.2 layer 4, a fluid organic substance, for example, a resist layer, is coated on the CVD SiO.sub.2 layer 4. The resultant body is subjected to an etch-back process, under the condition that the etching rate of the CVD SiO.sub.2 layer 4 is equal to that of the resist layer. The remaining resist layer is removed. Thus, the surface of the CVD SiO.sub.2 layer 4 is flattened. Thereafter, using a plasma CVD process, a CVD SiO.sub.2 layer 5 is further formed on the CVD SiO.sub.2 layer 4. A through-hole 8 reaching the first aluminum wire 11B is formed in the CVD SiO.sub.2 layers 4 and 5. Second aluminum wires 21A and 21B are formed on the CVD SiO.sub.2 layer 5. Consequently, the first aluminum wire 11B and the second aluminum wire 21B are electrically connected to each other through the through-hole 8.
According to the above process, the quality of the interlayer insulative layer is excellent; however, the flatness thereof is not satisfactory. Specifically, as is shown in FIG. 3, if the distance between the first aluminum wires 11A and 11B formed on the same plane is small, a cavity 10, which is called "nest", is formed in the CVD SiO.sub.2 layers 4 and 5. The cavity 10 makes it difficult to obtain the flat surface of the interlayer insulative layer.
In addition, the interlayer insulative layer may be formed, for example, by a bias sputtering process. In the bias sputtering process, however, sputtering and etching progresses simultaneously. Thus, if the distances between adjacent first aluminum wires differ from each other, the ratio of the degree of sputtering to the degree of etching varies in accordance with the different distances. Thus, since the thickness of the interlayer insulative layer varies in its portions located at spaces, there are problems in the shape of the interlayer insulative layer and the method of controlling the sputtering and etching. Furthermore, the interlayer insulative layer may be formed by means of a thermal oxidizing process. The interlayer insulative layer, formed by the thermal oxidizing process, has few pin holes and a high withstand voltage; however, the thermal oxidizing process requires high-temperature treatment and therefore wires may be damaged. Thus, the interlayer insulative layer formed by the thermal oxidizing process can be used only in limited locations.